1. Field of the Invention
This invention relates to field effect transistors utilizing enhancement-and depletion type devices.
2. Description of the Prior Art
Field effect transistors have enjoyed widespread use in various industries such as the data processing industry, particularly as large scale integrated circuits for around a decade. As compared to bipolar circuits, the main competitors of field effect transistors, the latter are much less expensive to fabricate. However, circuit operation with field effect transistors is a good deal slower than is achievable with bipolar circuits and a relatively higher magnitude of supply voltage is required to operate the field effect transistor circuits.
Various types of FET fundamental circuits have been proposed as solutions to these problems. The basic circuit is an inverter which may comprise, for example, a resistive type load interconnecting the drain voltage to the inverter output and an enhancement-type transistor connecting the output to the source of voltage. Due to the impracticality of providing a diffused region having a resistance sufficiently large to provide a low level of power dissipation without utilizing an enormous amount of semiconductor area, an enhancement-type field effect transistor in which the gate is connected to the drain supply voltage has been utilized as a substitute for the resistor. The disadvantage of this circuit is that the output voltage is limited to the drain voltage less the threshold voltage of the load transistor. In addition the output current of the load device decreases very rapidly as the magnitude of the voltage on the output, i.e., the source of the load transistor, increases.
Another family of circuits which are well known to those of skill in the art is the complementary inverter utilizing an N-channel enhancement-type transistor connected to the negative voltage supply and a P-channel enhancement-type transistor connected to the positive voltage supply, with the common drains being the output. This type of circuit uses substantial power only when the devices are switched and require only a single supply voltage. Their use is widespread in low power, relatively slow systems such as calculators, portable data buffers, and electronic watches. However, the use of transistors of opposite channel type necessitates an unusually large area on an integrated circuit chip due to the requirements of isolation between the devices. In addition, more processing steps are required, thereby significantly increasing fabrication costs.
More recently, circuit families have been proposed which employ as an inverter an enhancement-type field effect transistor (E-FET) connected between source and drain supply voltages with a depletion-type transistor (D-FET) as a load.
As is well known to circuit designers, an enhancement-type FET has substantially zero channel conductivity for zero gate-source voltage; the channel conductivity may be increased by applying a gate-source voltage of appropriate value. For an N-channel enhancement-type FET, a more positive gate-source voltage, denoted V.sub.G, or V.sub.GS, increases channel conductivity. A depletion-type FET, on the other hand, has appreciable channel conductivity for zero V.sub.G ; the channel conductivity may be increased or decreased according to the polarity of the V.sub.GS. For an N-channel depletion type FET, a more positive V.sub.GS increases channel conductivity; conduction continues until a predetermined negative V.sub.GS is applied.
The combination of an E-FET and a D-FET as an inverter is superior to an inverter employing E-FET's only, because the efficiency is higher and the transient response faster. It has been found that the current through the D-FET remains substantially constant as the output voltage transitions go toward the drain supply voltage, thus providing significantly greater switching speeds. The D-FET can also be made significantly smaller than an E-FET used for the same purpose, particularly where additional switching speed is not required.
As will be understood by those working in this field; such inverter circuits are seldom used individually; ordinarily, combinations of such circuits are formed as memory or logic circuits. Such combinations have revealed problems which have heretofore not been satisfactorily resolved, as for example, the power required and the performance obtainable.
For example, the operation of field effect transistor digital circuits is highly dependent on the ratio of current flowing through the transistors when the devices are supplied with a logic 1 or 0 input signa A typical line driver features an output stage comprising a series-connected D-FET and E-FET. The input signal is applied to the E-FET; and the D-FET input is controlled by a series connection of another E-FET and a D-FET load device. The input signal is also applied to the gate of the latter E-FET. The rise time and delay of the circuit is determined by the current generated by the output D-FET. To speed up circuit operation the output D-FET can be made wider, but this increases the power utilized in the low output state.
As another example, a four-device, static memory cell has been developed which utilizes a pair of E-FET's as a cross-coupled storage cell and a pair of double-threshold FET's functioning both as load as well as I/O devices. Such a memory cell is described in the publication by D. W. Kemerer entitled "Storage Cell Using Double-Threshold Field-Effect Transistors," IBM Technical Disclosure Bulletin, Vol. 14, No. 4, September 1971, pages 1077-78. This type of cell is superior to the more common six device static cells in that the chip space allocation required for each cell is considerably reduced through the use of double-threshold field-effect transistors. All of the devices described in the publication are of the enhancement type in that the devices are normally non-conducting until an appropriate bias is placed on their gate electrodes. The switching speed of this type of array is too low to be useful in commercially acceptable memory arrays. In addition, the biasing for the word line during cell operation is more complicated than for standard cells.